The present invention relates to shallow trench isolation (STI) processes employed in the fabrication of integrated circuits (ICs). The present invention more particularly relates to modified shallow trench isolation (STI) processes that include forming composite layered stacks become chemical-mechanical polishing of the integrated circuit (IC) substrate surfaces.
As the current IC technology moves to smaller feature sizes and the density of IC features in an IC substrate surface increases, STI processes are replacing the local oxidation of silicon (LOCOS) isolation methods as the process of choice for isolating active areas in Complementary Metal Oxide Semiconductor (CMOS) circuits, for example. Local oxidation of silicon (LOCOS) isolation methods are undesired at sub-0.5 xcexcm dimensions and lower because they typically introduce non-planarity and a xe2x80x9cbird""s beakxe2x80x9d at the edge of an active area and therefore reduce the packing density of the circuitry. In contrast, STI processes provide isolation schemes that produce a relatively high degree of planarity and eliminate the bird""s beak to dramatically reduce the chip area required for isolation.
FIGS. 1A-C show some major steps of a conventional STI process that may be employed to fabricate trenches in the IC substrate. In order to form a partially fabricated IC substrate 10 (hereinafter referred to as xe2x80x9cIC substratexe2x80x9d) as shown in FIG. 1A, a native oxide layer 24, e.g., a silicon dioxide layer, is blanket deposited on a surface of an IC substrate layer 12. A polishing stopping mask layer 14, e.g., a silicon nitride layer (Si3N4), is then blanket deposited over native oxide layer 24.
Next, polishing stopping layer 14, native oxide layer 24 and IC substrate layer 12 are etched through using conventional photolithography techniques well known to those skilled in the art to form trenches 18, 20 and 22 in IC substrate layer 12. Trench 22 is formed in a wide open area and trenches 18 and 20 are formed in a dense area of IC substrate 10. The dense area, as shown in FIG. 1A, has a greater number of trenches per unit area of the IC substrate surface than the wide open area. Those skilled in the art will also recognize that the trenches in the wide open area are also wider than the trenches in the dense area.
An insulating layer 16, e.g., a silicon dioxide layer, is then deposited either by chemical vapor deposition (CVD) or spin-on glass (SOG), for example, on IC substrate 10 filling trenches 18, 20 and 22 with the insulating layer so that subsequently formed active areas in IC substrate 10 are electrically isolated from each other. As shown in FIG. 1A, a portion of insulating layer 16 is also deposited above polishing stopping layer 14 and this portion of insulating layer 16 is referred to as the xe2x80x9cinsulating layer overburden.xe2x80x9d
IC substrate 10 is then subject to chemical-mechanical polishing (CMP) to remove the insulating layer overburden and polishing stopping layer 14. CMP typically involves mounting an IC substrate face down on a holder and rotating the IC substrate face against a polishing pad mounted on a platen, which in turn is rotating or is in orbital state. Those skilled in the art will recognize that because insulating layer 14 typically includes SiO2, xe2x80x9coxide CMPxe2x80x9d (which refers to the CMP process for polishing SiO2) is typically carried out in this step. During oxide CMP, a slurry composition including H2O2 (hydrogen peroxide), for example, is introduced between the polishing pad and an IC substrate surface or on the polishing pad near the IC substrate to remove SiO2.
FIG. 1B shows an intermediate structure that is formed during oxide CMP after the insulating layer overburden is removed and polishing stopping layer 14 is exposed. The presence of polishing stopping layer 14 ensures that after oxide CMP has concluded, an appropriate thickness of native oxide layer 24 is maintained above IC substrate layer 12. Those skilled in the art will recognize that a thickness of a native oxide layer has a significant impact on the performance characteristics of an IC.
As shown in FIG. 1B, after the insulating layer overburden is removed, the surface of insulating layer 16 above trenches 18 and 20 is substantially planar. Above trench 22, however, near or about a middle region of the surface of insulating layer 16 (in the wide open area), a concave region or an indented region 26 may be formed. Concave region 26 recesses inwardly into the surface of insulating layer 16 and is referred to as xe2x80x9cdishingxe2x80x9d because the profile of the concave region resembles the profile of a dish. The degree of dishing can be quantified by measuring the distance between the center of the surface of insulating layer 16 (above trench 22), which is typically the lowest point of the concave region, and the point where the insulating layer levels off, which is typically the highest point of the concave region.
After oxide CMP has concluded and polishing stopping layer 14 is removed, isolation structures (i.e. trenches 18, 20 and 22 filled with insulating material 16) are formed below the IC substrate layer 12, native oxide layer 24 with the appropriate thickness is maintained above the IC substrate layer and the substantially planar surface of insulating layer 16 above trenches 18 and 20 is preserved, as shown in FIG. 1C. The degree of dishing, however, in the wide open area above trench 22 may increase and the resulting concave region shown in FIG. 1C by reference numeral 26xe2x80x2 may recess inwardly into the surface of insulating layer 16 to a greater extent because during oxide CMP a material removal rate of the insulating layer (e.g., SiO2) is higher than a material removal rate of the polishing stopping layer (e.g., Si3N4). Thus, oxide CMP has a high selectivity to the polishing stopping layer. After the isolation structures shown in FIG. 1C are formed the IC fabrication process typically proceeds to forming IC features of active areas, e.g., transistor devices.
Unfortunately, the conventional STI process described above fails to provide trench isolation structures that effectively isolate active areas from each other. By way of example, the undesirable effect of dishing described above in detail may provide an electrically conductive pathway to charge carriers in a CMOS circuitry between a p-type doped region that may be disposed on one side of trench 22 and a n-type doped region that may be disposed on the other side of trench 22. As a result, electrical leakage over a period of time may result to catastrophic IC failure.
What is therefore needed is an improved STI process that reduces the likelihood of dishing and produces isolation structures or trenches filled with an insulating material having substantially planar surfaces that effectively isolate active areas in an IC from each other.
To achieve the foregoing, in one aspect, the present invention provides a process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material. A yet another step of the process includes polishing the integrated circuit substrate surface to remove a substantial portion of the composite layered stack and a portion of the insulating material adjacent to the composite layered stack at about a same rate. The polishing step facilitates in forming a substantially planar surface of the insulating material above the trench and reducing a likelihood of forming of a concave region near a middle region of the surface of the insulating material. The concave region recesses inwardly into the surface of the insulating material in the trench.
The process ma)y further include forming a plurality of transistors in the integrated circuit substrate and the plurality of the transistors are electrically isolated from each other by a plurality of the trenches. The integrated circuit substrate may be a semiconductor wafer substrate. The process may further still include depositing a layer of native oxide on the integrated circuit substrate surface before defining the masking layer and the step of etching in the above-described process through the composite layered stack includes etching through the native oxide layer to form the trench. The process may further still include removing the masking layer from the layer of the first material by wet etching or ashing.
The step of defining the masking layer on the composite layered stack may includes: (1) blanket depositing the polish stopping layer above the integrated circuit substrate surface; (2) blanket depositing the layer of the first material on the polish stopping layer to form the composite layered stack; (3) blanket depositing the masking layer on the layer of the first material; and (4) exposing the masking layer to a light source and developing the masking layer to define the mask on the layer of the first material. The layer of the first material includes at least one material selected from the group consisting of tungsten, doped silicon dioxide (e.g., borophosphosilicate glass or phosophosilicate glass containing boron or phosphorous from between about 0.1% and about 90%) and polymer and the polishing stopping layer includes at least one material selected from the group of silicon nitride and silicon oxynitride (e.g., SiOxNy or SiON).
A chemical-mechanical polishing removal rate of the layer of the first material is faster than a chemical-mechanical polishing removal rate of the insulating layer, e.g., silicon dioxide, by between about 50% and about 200%. The step of depositing the insulating material may include depositing a layer of silicon dioxide.
In one embodiment of the present invention, the step of polishing the integrated circuit substrate surface includes: (1) a first stage of chemical-mechanical polishing in which polishing is performed under conditions that produce a higher material removal rate of the layer of the first material than a material removal rate of the insulating material disposed adjacent the layer of the first material; and (2) a second stage of chemical-mechanical polishing in which polishing is performed under conditions that promote a higher material removal rate of insulating material disposed adjacent the polishing stopping layer than a material removal rate of the polishing stopping layer.
The above-described step of polishing may further include a pre-first stage of chemical-mechanical polishing that is performed before the first stage of chemical-mechanical polishing for removing the insulating material disposed above the composite layered stack. A substantial portion of the patterned composite layered stack may be exposed after the pre-first stage of chemical-mechanical polishing concludes.
In one embodiment where the layer of the first material includes at least one material selected from the group consisting of tungsten, doped silicon dioxide (e.g., borophosphosilicate glass or phosophosilicate glass containing boron or phosphorous from between about 0.1% and about 90%) and polymer and the insulating material includes silicon dioxide, a slurry composition that includes Fe(NO3)3 may be employed in the first stage of chemical-mechanical polishing. Furthermore, the polishing stopping layer includes silicon nitride and the insulating material includes silicon dioxide, a slurry composition that includes H2O2 may be employed in the second stage of chemical-mechanical polishing.
The process of fabricating a trench filled with the insulating material may be a shallow trench isolation process. The trench formed from one embodiment of the inventive process is a trench located in a wide open area on the integrated circuit substrate surface and the wide open area is different from a dense area that includes a greater number of trenches per unit area of integrated circuit substrate surface than the wide open area.
The polishing stopping layer may have a thickness that is between about 2,000 and about 20,000 Angstroms. The layer of the first material may have a thickness that is between about 50% and about 1000% of the thickness of the polishing stopping layer.
In another aspect, the present invention provides a partially fabricated integrated circuit substrate. The a partially fabricated integrated circuit substrate includes: (1) a trench formed in a surface of the partially fabricated integrated circuit substrate; (2) a composite layered stack disposed above a region to be protected on the partially fabricated integrated circuit substrate, the composite layered stack includes a layer of a soft material and a polishing stopping layer; and (3) an insulating layer deposited on the integrated circuit substrate surface filling the trench, wherein a film removal rate of the layer of the soft material is higher than the film removal rate of the insulating layer when the partially fabricated integrated circuit substrate surface is subjected to chemical-mechanical polishing.
The partially fabricated integrated circuit substrate may further include a native oxide layer disposed above the integrated circuit substrate surface and below the composite layered stack. The insulating layer may extend above the composite layered stack. The layer of the soft material may include at least one material selected from the group consisting of tungsten, doped silicon dioxide (e.g., boropllosphosilicate glass or phosophosilicate glass containing boron or phosphorous from between about 0.1% and about 90%) and polymer. The polishing stopping layer may include silicon nitride and silicon oxynitride. The insulating layer may include silicon dioxide. The polishing stopping layer may have a thickness of between about 2,000 and about 20,000 Angstroms. The layer of the soft material may have a thickness that is between about 50% and about 100% of the thickness of the polishing stopping layer.
The modified trench fabrication processes of the present invention represent a marked improvement over the conventional trench fabrication process. By way of example, the present invention reduces the likelihood that the surface of insulating layer above the trench in the wide open area will suffer from dishing. Thus, the trenches fabricated according to the present invention effectively electrically isolate active areas of an IC from each other. Furthermore, the likelihood of encountering problems associated with current leakage is also reduced.